To maximize computer performance, systems designers have long sought techniques that minimize the time required for instruction execution. Performance gains are promoted by hardware architectures that include a plurality of functional units, vector registers, scalar registers, address registers, and instruction buffers. In order to justify the cost of these expensive components, they must be kept reasonably busy. Parallel instruction execution represents an effort to increase the utilization of resources within a single processor.
In some computers, the instruction issue process involves checking the reservation flags for the resources involved in the operation during the clock period when the instruction is scheduled to issue. The instruction waits in the issue position until all of the required resources are available. Immediately upon instruction issue the reservation or busy flags are set for the assigned resources by the instruction issue control. Thereafter, subsequent instructions test these reservation flags immediately prior to issue and hold at the issue position if a resource conflict occurs.
In most computers, instruction issue occurs at every clock period if there is no resource conflict. Typically, the clock speed is slow enough that all necessary conflict checks, followed by instruction issue, can occur within one clock period. As clock speeds increase, however, there is not enough time in one clock period to resolve all the conflicts and then issue the instruction.
One such computer is the Cray 2 supercomputer built by Cray Research, Inc., the Assignee of the present invention. Because of propagation and fan-out delays caused by a four nanosecond system clock, the Cray 2 requires two clock periods to complete the "test and issue" sequence of testing for resource conflicts and then issuing the instruction. Therefore, the maximum instruction issue rate of the Cray 2 is one instruction every two clock periods.